In order to provide a clearer picture in which to contextualize embodiments of the invention, useful reference may be made to the block diagram represented in FIG. 1, which is a block diagram of a voltage regulator designed to drive a load L through a voltage regulator VR, controlled by means of two electronic switches (typically two MOSFETs) set between a supply voltage VIN and the ground G, with the function, respectively, of high-side switch HS and low-side switch LS.
The configuration represented in FIG. 1 is provided purely by way of example of a possible context for application of embodiments of the invention and hence must not be understood as in any way limiting the scope of the invention itself.
Usually, the voltage regulator VR is driven through the collectors or drains of the two high-side and low-side MOSFETs (or equivalent components) HS and LS, connected to one another, while the corresponding driving terminals (bases or gates) are driven by a driver D that receives a PWM driving signal from a controller C. The input of the controller is derived from an error amplifier EA, which detects the deviation between a reference voltage VREF and a feedback signal F drawn from the load L through a feedback line F.
Basically, the PWM signal output from the controller C drives the switches HS and LS, enabling transfer of the energy from an input represented by the supply voltage VIN to an output represented by the load L.
The voltage-regulator diagram represented in FIG. 1, which, as has been said, has a character purely of example, comprises in itself various possible alternative solutions. In particular, in the case of topologies of a double-ended type, such as the ones referred to as half-bridge or active-clamp topologies, the control of the switches HS and LS occurs in a complementary way. In particular, for half-bridge topologies, the complementary or asymmetrical control is actuated so as to obtain zero-voltage switching (ZVS) of the electronic switches HS and LS. Since the latter are usually components, such as MOSFETs, in order to guarantee that zero-voltage switching occurs, it is necessary to introduce between turning-off of one of the MOSs and turning-on of the other a dead time, which can be programmed to a desired value.
A solution commonly adopted in controllers for double-ended topologies with complementary driving envisages external programmability of the dead time by using a dedicated pin, to which a resistor is connected. A solution of this type is described in the National Semiconductor data sheet “LM 5025 Active Clamp Voltage Mode PWM Controller”, March, 2004, which is incorporated herein by reference.
Alternatively, instead of using a dedicated pin, it is possible to consider exploiting a pin that enables locking of a frequency of an oscillator. A solution of this type is described in the publication by George E. Danz “HP5500 High Voltage (500VDC) Power Supply Driver IC” Intersil Intelligent Power, December 1993, which is also incorporated herein by reference. As described in this publication, it is possible to consider making the oscillator by programming it externally through a resistive-capacitive (RT-CT) network that generates a sawtooth waveform. During the descending ramp of the sawtooth, a clock pulse is issued, which can be used as dead time.
This behavior is schematically represented in the diagrams of FIG. 2. In particular, FIG. 2 is constituted by four superimposed diagrams, designated, respectively, by a, b, c, and d, referred to one and the same time scale t on the abscissa. The uppermost diagram, designated by a, represents the sawtooth waveform generated by the resistive-capacitive network in question. As regards the block diagram of FIG. 1, this network can be viewed as being in the controller C, even though it is usually external to the controller to enable programmability of the oscillator.
The diagram designated by b corresponds to a train of clock pulses used for generating the dead time Tdead. The pulse train, which is also generated within the controller C, can be treated (via a logic circuit in the controller C) in such a way as to separate the even pulses E from the odd pulses O.
The aim again here is to use the leading edge of the odd pulses O to turn off the low-side MOS LS and the trailing edges of the same pulses to turn on the high-side MOS HS. Furthermore, as described in the publication by George E. Danz cited previously, it is possible to consider using the leading edge of the even pulses E to turn off the high-side MOS HS and the trailing edge of the same pulses to turn on the low-side MOS LS. In this way, between turning-off of one MOS and turning-on of the other, there elapses the same time, and moreover the even pulses E limit the maximum time of conduction of the high-side MOS HS and guarantee that the maximum duty cycle is less than 50%.
This type of behavior is represented in the further diagrams of FIG. 2 designated by c and d. The corresponding waveforms represent the waveforms that the driver D applies to the gate of the low-side MOS LS (diagram c) and to the gate of the high-side MOS HS (diagram d).
In diagrams b, c and d of FIG. 2, the symbols H and L obviously designate a logic signal of a “high” level and a “low” level, respectively. It may be noted that the switching frequency fsw is exactly half that of the sawtooth signal of the oscillator and that, during the time intervals designated by Tdead, both of the MOSs HS and LS are off.
By adopting this solution, the behavior of the circuit is in effect fixed in a rigid way by the train of clock pulses. The system described in the Danz publication functions in the way described above, guaranteeing that the two time intervals introduced between turning-off of one MOS and turning-on of the other are equal (because they are obtained once again starting from the clock). In this case, the MOS HS is always turned off by the clock.
In the case where it were necessary to turn the MOS HS off before (for example, via a signal generated by a control loop), it is no longer possible to use the trailing edge of the even pulse of the clock to turn on the MOS LS after the time Tdead because turning-off of the MOS HS would occur at an instant that is asynchronous with respect to the clock.
There exist applications in which it is effectively required that the high-side MOS HS be turned off in response to the control loop, in other words by a completely asynchronous signal. In these conditions of asynchronous operation, to turn on the low-side MOS LS after the dead time equal to the one introduced between turning-off of the low-side MOS LS and turning-on of the high-side MOS HS, it is not possible to use the even pulses E of the clock signal of diagram b.